1. Field of the Invention
The present invention relates to the construction of isolation region in integrated circuits, and particularly relates to the construction of isolation regions in silicon on insulator, SOI, structures.
2. Description of the Related Art
Silicon on insulator, SOI, is fast becoming the technology of choice for high performance MOS integrated circuits. Circuits constructed on SOI wafers are more resistant to high voltage damage (such as from drain-to-source punch through), are relatively immune from latchup problems, and have less parasitic capacitance as compared to bulk or epitaxial wafers. However, SOI wafers are more expensive, and thus any reduction in the production of SOI based circuits is of importance in reducing cost.
With reference to FIG. 1, a SOI wafer 11 is characterized by an insulator layer 13 buried under its top semiconductor layer 17. Buried insulator layer 13 separates the bulk substrate silicon region 15 from the top active silicon region 17, within which integrated circuits are constructed. As shown in FIG. 2, top layer 17 needs to be divided into active regions 19, within which circuits are constructed, separated by insulation regions 21. Thus, an initial step in the construction of any integrated circuit on a SOI wafer is to subdivide the wafer into active regions and insulation regions.
A preferred insulation method used in SOI technology is shallow trench isolation, STI, which provides a planar surface for further processing and avoids some of the problems inherent to less geometrically defined isolation structures, such as bird's beak issues found in LOCOS isolation.
There are various method of constructing a SOI wafer, including Silicon-On-Sapphire (SOS), Separation by Implanted Oxygen (SIMOX), and wafer bonding (WB). Of these three, SIMOX is the most commonly used method.
With reference to FIG. 3, a typical manufacturing process for constructing shallow trench isolation regions in a SOI wafer starting with a SIMOX process begins with a high dose implantation of oxygen ions O+ (˜2×1018/cm2) at a high energy of about 150-300 keV. This results in a layer 22 of buried oxygen ions O+ deep under the surface of the silicon wafer 11. This ion implantation step is typically executed at a temperature greater than 400° C. to ensure that the silicon maintains its crystallinity during the implantation.
Wafer 11 is then subjected to a heat anneal step (˜3-5 hours), preferably in an N2 atmosphere, at a high temperature of about 1100-1175° C. This permits the buried oxygen ions O+ to diffuse and recombine with the silicon to produce a buried oxide layer (SiO) as shown in FIG. 4, and additionally helps to remove any defects that may have been created during the ion implantation step. This process results in a typical top silicon layer of about 0.5 μm. If a top layer thicker than can be practically achieved by the ion implantation depth is desired, then an optional epitaxial silicon layer, not shown, may be deposited on the top silicon layer 17. At this point, construction of the SOI wafer structure is complete and construction of the isolation regions can begin.
With reference to FIG. 5, construction of the shallow trench isolation regions begins by growing a padding layer of oxide 21, followed by a deposition of a silicon nitride layer 20 by LPCVD, as shown in FIG. 6. Silicon nitride layer 20 is then configured into a mask layer 23 by means of a resist, as shown in FIG. 7. The pad oxide 21 in exposed regions is likewise removed in FIG. 7. Mask layer 23 covers the intended active regions, and exposes the areas where isolation trenches are to be constructed.
In FIG. 8, trenches 24 are form in an anistropic-etching step, typically to a depth of about 400-500 nm. This is followed by growth of a thin thermal oxide layer 25 within trenches 24.
In FIG. 9, a CVD dielectric layer 27 is deposited to fill the trenches. Dielectric layer 27 also covers silicon nitride layers 23. The wafer is then subjected to a chemical mechanical polishing step, CMP, to polish back dielectric layer 27, with silicon nitride layer 23 functioning as a CMP-stop layer, as shown in FIG. 10. The dielectric material is typically then densified at 900° C. Finally in FIG. 11, the silicon nitride is stripped, leaving the desired STI structure of active regions 19 separated by shallow trench isolation regions 21.